Worked example

One research paper, one editable talk: the SANGAM example

We gave Dekked an open-access paper, SANGAM, which generates SystemVerilog assertions for chip designs with a Monte Carlo tree search, and asked for a conference-style talk. Below, figures and a table from the paper sit next to the slides Dekked built from them.

The 10-slide deck is a normal PowerPoint file: download it and edit any text, shape or chart in PowerPoint; it also opens in Keynote and Google Slides. No sign-up needed.

Download the deck (.pptx, 4.2 MB) Read the paper on arXiv

What you are looking at

Deck shown: Premium plan, with small fixes made in PowerPoint.

Dekked generated the deck. Before publishing it we made four small fixes by hand:

Slide 2: Two text blocks ran their sentences together, so we split them into separate lines. A statistic in the “hand-written SVAs” card was misplaced (18 is SANGAM’s own result for one signal in Table I); we replaced it with the number of I2C signals Table I evaluates, 23.
Slide 4: One arrow pointed the wrong way. It now runs from the Waveform Analyzer into the information bank, as Section III-A of the paper describes.
Slide 6: We renamed three of the chart’s group labels to match Table I’s signal groups (Clock/Reset, IO control, IO data) and corrected the footnote from 24 to 23 signal rows, along with the matching speaker note.
Slide 9: Two text blocks ran their sentences together, so we split them into separate lines.

Everything else is as Dekked generated it. Slides 1 and 10 use AI-generated background images, as Premium decks may. We reduced the file size by compressing the embedded images; the slides themselves are unchanged.

The paper

Adarsh Gupta, Bhabesh Mali, Chandan Karfa. “SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine.” arXiv:2506.13983, June 2025. Licensed under CC BY 4.0.

The figures and table below are cropped from the paper under that licence, and the slides are adapted from it by Dekked. The authors are not affiliated with Dekked, and nothing on this page implies their endorsement.

The paper next to the deck

Each pair shows a figure or table as it appears in the paper, then the slide Dekked made from it.

Figure 1 of the SANGAM paper: the proposed architecture in three stages — specification processing, assertion reasoning and assertion combination. — The paper’s architecture figure is placed on the slide as the authors drew it, and the three stages are summarized in cards underneath.

Slide 3 of the Dekked deck: “Three stages turn specs, waveforms and architecture into per-signal SVAs”. — The paper’s architecture figure is placed on the slide as the authors drew it, and the three stages are summarized in cards underneath.

Figure 2 of the SANGAM paper: the four phases of each Monte Carlo tree search rollout — select, expand, evaluate and back-propagate. — The rollout figure is placed on the slide, with the four phases (select, expand, evaluate, back-propagate) written out beside it.

Slide 5 of the Dekked deck: “MCTSr rolls out four phases to refine each signal's assertions”. — The rollout figure is placed on the slide, with the four phases (select, expand, evaluate, back-propagate) written out beside it.

Table I of the SANGAM paper: correct assertions per I2C signal for SANGAM and AssertLLM, 152 versus 50 in total. — Table I’s 23 signal rows are summed into four groups and drawn as a native PowerPoint chart: SANGAM vs AssertLLM, 35 vs 3, 21 vs 4, 53 vs 11 and 43 vs 32 (152 vs 50 in total). Double-click it in PowerPoint to edit the numbers. The group labels are one of the hand fixes listed above.

Slide 6 of the Dekked deck: “152 correct assertions on I2C — three times AssertLLM's 50”. — Table I’s 23 signal rows are summed into four groups and drawn as a native PowerPoint chart: SANGAM vs AssertLLM, 35 vs 3, 21 vs 4, 53 vs 11 and 43 vs 32 (152 vs 50 in total). Double-click it in PowerPoint to edit the numbers. The group labels are one of the hand fixes listed above.

Figure 3 of the SANGAM paper: branch, property and toggle coverage for the I2C and RV-Timer designs. — The coverage chart’s six values (branch, property and toggle coverage for I2C and RV-Timer) are redrawn as a native, editable PowerPoint chart, grouped by coverage type.

Slide 7 of the Dekked deck: “Above 90% branch and toggle — ChIRAAG never proves the branch”. — The coverage chart’s six values (branch, property and toggle coverage for I2C and RV-Timer) are redrawn as a native, editable PowerPoint chart, grouped by coverage type.

All 10 slides

Slide 1. A tree search that writes chip assertionsAI-generated background image.
Slide 2. Hand-written assertions are slow — and one-pass LLMs miss the signalFixed by hand in PowerPoint (see above).
Slide 3. Three stages turn specs, waveforms and architecture into per-signal SVAs
Slide 4. Three LLM agents build a signal-wise information bankFixed by hand in PowerPoint (see above).
Slide 5. MCTSr rolls out four phases to refine each signal's assertions
Slide 6. 152 correct assertions on I2C — three times AssertLLM's 50Fixed by hand in PowerPoint (see above).
Slide 7. Above 90% branch and toggle — ChIRAAG never proves the branch
Slide 8. A full run costs $16.01 in DeepSeek-R1 API — about $0.49 per signal
Slide 9. No inter-signal irredundancy guarantee — and three next movesFixed by hand in PowerPoint (see above).
Slide 10. Tree search finds the assertions a single pass cannotAI-generated background image.